The present invention relates generally to static random access memories, and more particularly to a high performance domino static random access memory (SRAM) with a split local bitline and a continuous bitline.
High performance domino SRAMs are known in the art. For example, U.S. Pat. No. 5,668,761 discloses a high performance domino SRAM.
FIGS. 1A and 1B illustrates a high performance, low power domino SRAM design including multiple local cell groups. As shown in FIG. 1A, each cell group includes multiple SRAM cells 1-N and local true and complement bitlines LBLT and LBLC. Each SRAM cell includes a pair of inverters that operate together in a loop to store true and complement (T and C) data. The local true bitline LBLT and the local complement bitline LBLC are connected to each SRAM cell by a pair of wordline N-channel field effect transistor (NFETs) to respective true and complement sides of the inverters. A WORDLINE provides the gate input to wordline NFETs. A particular WORDLINE is activated, turning on respective wordline NFETs to perform a read or write operation.
As shown in FIG. 1B, the prior art domino SRAM includes multiple local cell groups 1-M. Associated with each local cell group are precharge true and complement circuits coupled to the respective local true and complement bitlines LBLT and LBLC, write true and write complement circuits, and a local evaluate circuit. Each of the local evaluate circuits is coupled to a global bitline labeled 2ND STAGE EVAL and a second stage inverter that provides output data or is coupled to more stages. A write predriver circuit receiving input data and a write enable signal provides write true WRITE T and write complement WRITE C signals to the write true and write complement circuits of each local cell group.
A read occurs when a wordline is activated. Since true and complement (T and C) data is stored in the SRAM memory cell, either the precharged high true local bitline LBLT will be discharged if a zero was stored on the true side or the precharged high complement bitline LBLC will be discharged if a zero was stored on the complement side. The local bitline, LBLT or LBLC connected to the one side will remain in its high precharged state. If the true local bitline LBLT was discharged then the zero will propagate through one or more series of domino stages eventually to the output of the SRAM array. If the true local bitline was not discharged then no switching through the domino stages will occur and the precharged value will remain at the SRAM output.
To perform a write operation, the wordline is activated as in a read. Then either the write true WRITE T or write complement WRITE C signal is activated which pulls either the true or complement local bitline low via the respective write true circuit or write complement circuit while the other local bitline remains at its precharged level, thus updating the SRAM cell.
SRAM arrays are typically used for applications requiring high capacity. SRAM storage cells are typically designed for very high density to accommodate this high capacity. Often the feature sizes inside the SRAM cell are the densest allowed in a given technology. Therefore since the cell is designed to be small, little room exists to place wires within the pitch of the SRAM cell. It is not uncommon for there to be only room enough for two or three wiring tracks available over the SRAM cell in each X and Y direction. Since power and ground connections must also be made to each SRAM cell, this puts the number of wires available at a premium. Anything that can reduce the number of wires required will result in savings in area and power.
The prior art domino SRAM array typically has one wire for the wordline in the Y direction. A total of five wires are provided in the X direction including the true and complement local bitlines LBLT, LBLC, the global bitline, and the true and complement write lines, WRITE T and WRITE C.
Typically the SRAM cell width is not large enough to accommodate this number of wires on the same wiring level so that some of the wires must be moved up to higher wiring levels. A problem of such multiple level wiring arrangement is that other circuits on the chip are prevented from using those wiring areas.
A need exists for a high performance domino static random access memory (SRAM) that reduces the number of wires required. It is also desirable to provide a high performance domino static random access memory (SRAM) that minimizes power consumption and area requirements.
A principal object of the present invention is to provide an improved high performance domino static random access memory (SRAM). Other important objects of the present invention are to provide such improved high performance domino static random access memory (SRAM) substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a high performance domino static random access memory (SRAM) is provided. The domino SRAM includes a plurality of local cell groups. Each of the plurality of local cell groups includes a plurality of SRAM cells and a local true bitline coupled to each of the plurality of SRAM cells of each local cell group. A continuous complement bitline is coupled to each of the plurality of local cell groups and is coupled to each of the plurality of SRAM cells of each local cell group.
In accordance with features of the invention, only driving the continuous complement bitline is required for a write to the SRAM cell complement node. The domino SRAM reduces the number of required wires and required transistors as compared to prior art domino SRAMs and thus the area needed and power consumption are reduced for the domino SRAM.